Line Driver With Tuned On-Chip Termination

ABSTRACT

A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver&#39;s output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver&#39;s gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

FIELD OF THE INVENTION

This invention relates to line (output) drivers for integrated circuits(ICs), and in particular to line drivers with on-chip termination.

BACKGROUND OF THE INVENTION

Line (output) driver circuits providing on-chip termination (i.e. usingits output impedance as termination) are capable of delivering the samevoltage swing with half of the power when compared with line driversusing external resistor termination. This power advantage arises becausethe on-chip termination line driver does not need to drive the externaltermination resistor.

FIG. 9 shows a basic prior art line driver circuit 30 that produces acontrolled termination resistance Row using voltage and currentfeedback. Line driver 30 is disclosed in U.S. Pat. No. 5,121,080, whichis incorporated herein by reference in its entirety. Line driver 30includes an amplifier 31 having an inverting input terminal connected toground (or a common mode voltage), a non-inverting input terminalconnected to a current driver 32, and an output terminal connected to anode 34. Current driver 32 includes a digital-to-analog converter (DAC)that generates a current signal I_(DAC) derived from an input signalreceived from a logic portion of the integrated circuit (not shown) onwhich line driver 30 is incorporated. Node 34 is connected to drive thegate terminals of a first P-channel transistor 36 and a second P-channeltransistor 37. The source-drain path of first P-channel transistor 36 isconnected between voltage source V_(DD) and an internal node 38, and thesource-drain path of second P-channel transistor 37 is connected betweenvoltage source V_(DD) and an output node 39, at which output voltageV_(OUT) is generated. Input node 38 is connected to the non-invertinginput terminal of amplifier 31 and to current driver 32, and a feedbackresistor R_(f) is connected between nodes 38 and 39.

In operation, line driver 30 is implemented to transmit data signals toa selected signal destination by way of a transmission line, which isrepresented in FIG. 9 by a load resistor R_(L) that is connected betweenthe output node 39 and ground. First transistor 36 forms the first stageof a current drive circuit that generates a current I₁ in response tothe output signal generated by amplifier 31, and transistor 37 forms asecond stage that is a “replica” of the first stage in that it is alsodriven by the output signal from amplifier 31, and generates a currentI₂ that is directly proportional to current I₁ of the first stage. Aratio between the two currents I₁ and I₂ generated by the two drivestages corresponds to an aspect ratio between transistors 36 and 37,which is set such that first transistor 36 is given a value of “1” andsecond transistor 37 is given a value of “N”. The output impedance ofamplifier 31 is a function of the current ratio between transistors 36and 37, as well as the value of the feedback resistor R_(f). Thisrelationship provides a constant ratio between the current drive and theoutput current. In essence, current drive is added to the summing nodeutilizing a replica of the first output stage, with the output impedancedepending upon the on-chip feedback resistance R_(f) such thatadjustment of either the feedback resistor R_(f) or the value of “N”,will allow adjustment of the output impedance, as represented below byEquation 1:

R _(OUT) =R _(f)/(1+N)   Eq. 1

Meanwhile, the transimpedance gain of driver circuit 30 is representedby Equation 2:

V _(OUT) =I _(DAC)·(N*R _(L))/2   Eq. 2

Note that Eq. 2 is true if R_(f)=(1+N)*R_(L), and Eq. 1 is satisfied.

A problem with line driver 30 is that the on-chip resistor R_(f) issubjective to process variation, and as a result, the output resistanceR_(OUT) will vary from chip to chip. Avoiding this problem requires amechanism for adjusting the output resistance R_(OUT) after fabricationin order to cause output resistance R_(OUT) to match load resistanceR_(L). From Equation 1, to make the output resistance R_(OUT) adaptive,those skilled in the art will recognize that the best approach is tocontrol (adjust) the values R_(f) or N, or both.

FIG. 10 shows another prior art line driver 40 that achieves aconsistent output resistance by utilizing a variable replica stage 47 toadjust the value of N in Eq. 1 (above). Output driver circuit 40 isdisclosed in U.S. Pat. No. 7,119,611 issued Oct. 10, 2006, which isincorporated herein by reference in its entirety. Similar to line driver30 (discussed above), line driver 40 includes an amplifier 41 having aninverting input terminal connected to ground, a non-inverting inputterminal connected to a current driver 42, and an output terminalconnected to drive the gate terminals of a first stage P-channeltransistor 46. The source-drain path of first P-channel transistor 46 isconnected to an internal node 48. Variable replica stage 47 includesmultiple transistors programmably connected in parallel such that theirsource-drain paths selectively connected between V_(DD) and output node49, which in operation is connected to a transmission line representedin FIG. 10 by a load resistor R_(L). Internal node 48 is connected tothe non-inverting input terminal of amplifier 41 and to current driver42 by way of a feedback resistor R_(F), and a series resistor R_(S) isconnected between internal node 48 and output node 49. The currentthrough variable replica stage 47 is a function of the number oftransistors that are connected in parallel, which is controlled by avalue stored in a calibration register (not shown). This value isdetermined by an analog engine during a calibration operation, whichdetermines the value of the output impedance R_(OUT) as a function ofthe series resistance R_(S) and the ratio of transistor 46 and theselected parallel transistors in variable replica stage 47. The ratiosof the transistor 46 and the parallel connected transistors in variablereplica stage 47 are defined such that a value of “1” is assigned forthe transistor 46 and a value of “N” is assigned for the selectedtransistors in variable replica stage 47, it being understood that thevalue of “N” can be varied by selecting different combinations oftransistors in variable replica stage 47.

Although line driver 40 provides advantages over line driver 30 (seeFIG. 9), it still presents a few problems. First, the variable replicastage arrangement provides a transimpedance gain defined in Equation 3:

V _(OUT) =I _(DAC)*[(R _(F) +N*R _(L))]/2   Eq. 3

Under the condition of R_(F)>>N*R_(L), as set forth in U.S. Pat. No.7,119,611, V_(OUT)=I_(DAC)*R_(F)/2. Second, the current I generated bytransistor 46 has to flow through series resistor R_(S), which resultsnot only in a voltage divider, but also a mismatch of V_(DS) (drain tosource voltage) between transistor 46 and variable replica stage 47,which causes line driver 40 to produce a nonlinear gain and thedistortion of matching ratio N.

The problems associated with line driver 40 are described with referenceto FIGS. 11(A) and 11(B). FIG. 11(A) is a simplified circuit showingportions of line driver 40 and depicts the cause of ½ gain issue. For aunit of current I flowing through transistor 46, there will be a N*Icopy flowing out of variable replica stage 47, making the total currentflow through load resistance R_(L) equal to (N+1)*I. This currentresults an equivalent resistor of (N+1)*R_(L). Notice that seriesresister R_(S) is also equivalent to (N+1)*R_(L), and as a result avoltage divider is formed that divides the gain by 2. So the outputvoltage V_(OUT) is half of amplifier output, as shown in 11(B) and setforth in Equation 4:

V _(OUT)=½V _(DAC)=½I _(DAC) *R _(F)   Eq. 4

What is needed is a line driver with on-chip termination that overcomesthe gain issues and other problems associated with prior art linedrivers.

SUMMARY OF THE INVENTION

The present invention is directed to a line driver with on-chiptermination that utilizes a bridge resistor to improve thetransimpedance gain by a factor of two over prior art line drivers, andutilizes an adjustable series resistor to facilitate adjusting theoutput resistance of the line driver in an efficient manner.

In accordance with a first embodiment, an IC includes line driver forgenerating a predetermined output voltage on an output node in responseto a digital data signal. When implemented in a system, the output nodeis connected to a transmission line having a load resistance R_(L),which is know (e.g., 75 Ω (Ohms)). The line driver utilizes a currentdriver and an amplifier to generate an output control signal in responseto the digital data signal. The output control signal is connected thegate terminals of a first stage transistor and a second stagetransistor. The source-drain path of the first stage transistor isconnected between a voltage source and an internal node, and thesource-drain path of the second stage transistor is connected betweenthe voltage source and an output node, at which output voltage isgenerated. The first stage transistor generates a first current at theinternal node in response to the output control signal, and second stagetransistor generates a second current at the output node that isdirectly proportional to the first current. A ratio between the twocurrents generated by the two drive stages corresponds to an aspectratio between the first and second stage transistors, which is set usingknown techniques such that the first stage transistor is given a unitvalue of “1” and the second stage transistor is given a value of “N”(e.g., ten). The series resistor is connected between the interior nodeand the output node, and a feedback resistor is connected between theinterior node and a non-inverting input terminal of the amplifier.

According to an aspect of the present invention, a bridge resistor isconnected between the internal node and the common mode (ground), and isprovided with a resistance value selected such that the an internalvoltage generated at the internal node is equal to the predeterminedoutput voltage generated at the output node, whereby substantially zerocurrent flows between the output node and the internal node through theseries resistor. In one specific embodiment in which current through thefeedback resistor is insignificant, the resistance value of the bridgeresistor is substantially equal to the aspect ratio value “N” times theload resistance R_(L). In another embodiment, where feedback resistanceis not negligible, the resistance value of the bridge resistor ismatched with the combined resistance value of the feedback resistor andthe load resistance to produce the desired internal node voltage. Byproviding the bridge resistor, a bridge-type circuit is formed such thatthe output voltage is the same as the internal node voltage generated bythe first stage transistor (i.e., there is no factor two degradation asin conventional line drivers), and the resistance value of the seriesresistor does not affect the output voltage, which makes the adjustmentof the output resistance completely independent of the driver's gain.

According to another aspect of the present invention, the seriesresistor is implemented by an adjustable resistor circuit includingseveral parallel trim units that are individually adjustable (trimmable)by way of control signals generated by a control circuit such that thedriver's output resistance matches the load resistance. In oneembodiment, the series resistor has a resistance value substantiallyequal to (1+N)*R_(L), where N denotes the aspect ratio of the first andsecond stage transistors, and where R_(L) denotes the load resistancevalue of the transmission line. In another embodiment, an additional“fixed” series resistor is connected to the output node, and the seriesresistor has a resistance value substantially equal to(1+N)*(R_(L)−R_(SL)), where R_(SL) denotes the resistance value of the“fixed” series resistor. The fixed series resistor is added mainly tofacilitate the function of echo cancellation, which if the output is afully differential circuit, it is fully cancelled at the receiving end.

According to another embodiment, a system includes an integrated circuithaving two associated line drivers that transmit differential signalsonto associated transmission lines, and also includes an echocancellation circuit that is connected between respective output nodesof the line drivers. The echo cancellation circuit establishes aresistive divider between the output terminals of the line drivers usingresistances that are proportional to resistance values of the linedrivers and transmission lines, but with a scale up factor. The echocancellation circuit provides output voltages that are independent ofthe output signals generated at the line driver output nodes, wherebyecho cancellation is achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings, where:

FIG. 1 is a simplified circuit diagram showing an integrated circuitincluding a line driver with on-chip termination according to anembodiment of the present invention;

FIGS. 2(A) and 2(B) are circuit diagrams showing simplifiedrepresentations of the line driver of FIG. 1;

FIG. 3 is a simplified circuit diagram showing a adjustable seriesresistor of the line driver of FIG. 1 according to a specific embodimentof the present invention;

FIG. 4 is a simplified circuit diagram showing a trim unit of theadjustable series resistor of FIG. 3 according to a specific embodimentof the present invention;

FIG. 5 is a simplified circuit diagram showing a line driver withon-chip termination according to another embodiment of the presentinvention;

FIG. 6 is a simplified circuit diagram depicting a fully differentialcircuit utilizing two line drivers shown in FIG. 5;

FIG. 7 is a simplified circuit diagram showing a tuner circuit fortuning a series resistor of the line driver of FIG. 5 according toanother embodiment of the present invention;

FIGS. 8(A) and 8(B) are circuit diagrams showing circuits for generatingreference voltages utilized by the tuner circuit of FIG. 7;

FIG. 9 is a simplified circuit diagram showing a conventional linedriver with on-chip termination;

FIG. 10 is a simplified circuit diagram showing another conventionalline driver with on-chip termination; and

FIGS. 11(A) and 11(B) are circuit diagrams showing simplifiedrepresentations of the line driver of FIG. 10.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention relates to an improvement in line drivers withon-chip termination. The following description is presented to enableone of ordinary skill in the art to make and use the invention asprovided in the context of a particular application and itsrequirements. The terms “coupled” and “connected”, which are utilizedherein, are defined as follows. The term “connected” is used to describea direct connection between two circuit elements, for example, by way ofa metal line formed in accordance with normal integrated circuitfabrication techniques. In contrast, the term “coupled” is used todescribe either a direct connection or an indirect connection betweentwo circuit elements. For example, two coupled elements may be directlyconnected by way of a metal line, or indirectly connected by way of anintervening circuit element (e.g., a capacitor, resistor, inductor, orby way of the source/drain terminals of a transistor). Variousmodifications to the preferred embodiment will be apparent to those withskill in the art, and the general principles defined herein may beapplied to other embodiments. Therefore, the present invention is notintended to be limited to the particular embodiments shown anddescribed, but is to be accorded the widest scope consistent with theprinciples and novel features herein disclosed.

FIG. 1 shows a simplified IC 100 including a generalized logic circuit101 for generating a digital signal DATA, and a line (output) driver 102for generating a predetermined output voltage VOW on a output node 145in response to digital signal DATA. When implemented in a system, outputnode 145 is connected to a transmission line TL having a load resistanceR_(L), which in the present case is known (e.g., a cable line with a 75Ω (Ohms)). IC 100, which includes both logic circuit 101 and line driver102, is formed on a semiconductor (e.g., monocrystalline silicon) “chip”using established semiconductor fabrication techniques. In contrast,transmission line TL is formed separate from IC 100, and is connected toan external pin or pad of IC 100, for example, by way of solderconnection.

Similar to conventional line drivers, line driver 102 utilizes a currentdriver 110 and an amplifier 120 to generate an output control signalCNTL in response to digital signal DATA. Current driver 110 includes adigital-to-analog converter (DAC) receives a digital signal DATA fromlogic portion 101 of IC 100, and generates a current signal I_(DAC) atan input node 141. Amplifier 120 has an inverting input terminalconnected to a common mode voltage V_(CM) (or ground), a non-invertinginput terminal connected to current driver 110 by way of a input node141, and an output terminal 122. With this arrangement, amplifier 120generates an output control signal CNTL on output terminal 122 inresponse to a digital data signal DATA. Output control signal CNTL isconnected to drive the gate terminals of a first P-channel transistor130 and a second P-channel transistor 135. The source-drain path offirst P-channel transistor 130 is connected between voltage sourceV_(DD) and an internal node 143, and the source-drain path of secondP-channel transistor 135 is connected between voltage source V_(DD) andan output node 145, at which output voltage V_(OUT) is generated. Inputnode 141 is connected to internal node 143 by way of a feedback resistorRF. First transistor 130 forms the first stage of a current drivecircuit that generates a current I at internal node 143 in response tothe output control signal CNTL, and transistor 135 forms a second stagethat is a replica, of the first stage in that it is also driven by theoutput control signal CNTL and generates a current NI (N times unitcurrent I) at output node 145 that is directly proportional to current Iof the first stage. A ratio between the two currents I and NI generatedby the two drive stages corresponds to an aspect ratio betweentransistors 130 and 135, which is set using known techniques such thatfirst transistor 130 is given a value of “1” and second transistor 135is given a value of “N”. A series resistor 155 is connected betweeninterior node 143 and output node 145.

According to an aspect of the present invention, a resistive path,indicated by bridge resistor 153, is added between internal node 143 andthe common mode (ground), and provides a resistance value R_(B)determined such that an internal voltage V₁₄₃ at internal node 143 issubstantially equal to output voltage V_(OUT) generated at the outputnode 145, whereby substantially zero current flows between output node145 and internal node 143 through series resistor 155. In the contextprovided herein the terms “substantially equal” and “substantially zero”are used to indicate that the resistance value R_(B) is set with theintention of producing zero voltage drop across series resistor 155,although minor variances due, for example, to process mismatch, maycause the resistance R_(B) to be not exactly equal to N*R_(L), resultingin a minor current flow (e.g., equal to 5% or less of the currentI_(DAC) generated by current source 110). Note that, without bridgeresistor 153, nearly all of the I_(DAC) current flows through seriesresistor 155, which causes a significant voltage difference betweeninternal node 143 and output node 145. By including bridge resistor 153in line driver 102 with a resistance value that balances the voltages atnodes 143 and 145, even with imperfections due to process variations,only a small fraction of the I_(DAC) current flows through seriesresistor 155, and the effect is negligible.

The main benefit achieved by the addition of bridge resistor 153 to linedriver 102 is that it improves the trans-impedance gain of line driver102 by a factor of two over the conventional line driver 40 (describedabove with reference to FIG. 10). In contrast, prior art line driver 40of U.S. Pat. No. 7,119,611 (see FIGS. 10, 11(A) and 11(B), discussedabove) is constructed such that most of the current has to flow throughresistor R_(S), which results not only in a voltage divider, but also amismatch of V_(DS) between transistors 45 and 47 (see FIG. 10), whichresults in nonlinear operation. As set forth above, in line driver 40,resistor R_(S) is a function of output gain in that, when resistor R_(S)is properly tuned, its resistance value equals (1+N)*R_(L), whichresults in a gain value of ½. Returning to line driver 102 (FIG. 1),because the resistance R_(B) of bridge resistor 153 is set such thatsubstantially zero current passes through series resistor 155, theresistance R_(S) of series resistor 155 is not part of the outputvoltage V_(OUT), (i.e., output voltage V_(OUT) is independent fromresistance R_(S) of series resistor 155), which allows adjustment ofoutput resistance R_(OUT) by way of series resistor 155 in manner thatis completely independent of the gain.

In one embodiment (i.e., where the resistance R_(F) of feedback resistor151 is substantially larger than the resistance of bridge resistor 153),bridge resistor 153 is fabricated to include a resistance that issubstantially equal to the value “N” times the expected load resistanceR_(L) (i.e., a resistance value of R_(L)N). For example, when linedriver 102 is fabricated such that the aspect ratio between transistor135 and transistor 130 is equal to 10, and is fabricated to generate apredetermined output voltage V_(OUT) on output node 145 when output node145 is connected to a transmission line having a resistance value R_(L)equal to 75 Ω, then bridge resistor 153 is fabricated with a resistancevalue R_(L)N substantially equal to 750 Ω.

FIGS. 2(A) and 2(B) are simplified representations of line driver 101when the resistance of bridge resistor 153 equals R_(L)N. As indicatedin FIG. 2(A), similar to the prior art circuit, when a unit of current Iflows through transistor 130, a current N*I flows through transistor135. The difference between output driver 101 and prior art driver 40(FIG. 10) is that all of the current I through transistor 130 flowsthrough bridge resistor 153, which develops a voltage drop of I*R_(L)Nat internal node 143. Similarly, all of the current NI throughtransistor 135 flows into load resistor R_(L), which develops an outputvoltage V_(OUT) that is equal to NI*R_(L) at output node 145. Becausethe voltages at both internal node 143 and output node 145 are the same,there is no voltage drop across resistor 155, and there is no netcurrent flow I_(RS) through series resistor 155. As a result, abridge-type circuit is formed, and output voltage V_(OUT) is the same asthe output voltage of transistor 135, and there is no factor twodegradation as in prior art line driver 40. That is, series resistanceR_(S) is not in the picture of the output voltage, which makes theadjustment of output resistance R_(OUT) completely independent of thegain. As such, as indicated in FIG. 2(B), series resistor 155 can be setequal to the load resistance value R_(L) times (1+N), which optimizesoutput impedance R_(OUT).

The embodiment described above where bridge resistor 153 has theresistance value R_(L)N assumes the resistance R_(F) of feedbackresistor 151 is much greater than the resistance value R_(L)N. Referringto FIG. 1, in this case the current that flows through feedback resistorR_(F) is negligible compared to the current passing through bridgeresistor 153. However, if the resistance R_(F) is smaller such that thecurrent through feedback resistor 151 becomes significant, then theresistance value of bridge resistor 153 would have to be increased(i.e., larger than R_(L)N) in order to maintain the objective ofminimizing current through series resistor 155. That is, in accordancewith an alternative embodiment of the present invention, the resistancesof feedback resistor 151 and bridge resistor 153 are matched to form abridge circuit that maintains voltage V₁₄₃ at internal node 143 equal tothe output voltage V_(OUT) (i.e., equal to I*R_(L)N).

According to another aspect of the present invention, series resistor155 is implemented using a trimmable resistive circuit that is connectedbetween internal node 143 and output node 145, and is controlled by atuner (control) circuit 160 that is integrally fabricated on IC 100 andgenerates control signals CN1, CN2 that are transmitted to seriesresistor 155, whereby series resistance R_(S) is adjustable such thatoutput impedance R_(OUT) of line driver 102 is set to match an appliedload impedance. For example, in the embodiment shown in FIG. 1, seriesresistance R_(S) is adjusted to equal (1+N)*R_(L), whereby outputimpedance R_(OUT) of line driver 102 is set to match the load impedanceR_(L) of transmission line TL. In other embodiments set forth below,series resistance R_(S) may be set to another value.

FIG. 3 is a simplified circuit diagram showing series resistor 155according to a specific embodiment of the present invention. Seriesresistor 155 includes parallel trim units 310-1 to 310-N, where eachtrim unit 310-1 to 310-N provides an associated adjustable (trimmable)resistance R_(TU1) to R_(TUN), respectively, and the combinedresistances provided by parallel trim units 310-1 to 310-N producesseries resistance R_(S).

FIG. 4 is a circuit diagram showing an exemplary trim unit 310-1, whichincludes a first resistor 401 and a second resistor 402, each having aresistance RT1, a first switch 403 connected in series with first andsecond resistors 401 and 402, and a third resistor 404 and second switch405 connected in parallel with first switch 403. Note that switches S1and S2 in each unit 310-1 to 310-N are implemented using CMOStransmission gates. Control signals C11 and C12 are transmitted to unitresistance trim unit 310-1 to selectively control switches S1 and S2,thereby providing fine control such that the combined equivalentresistance R_(S) between internal node 143 and output node 145 is withina predetermined range of the desired series resistance value R_(S). Inthe specific embodiment shown in FIG. 3, each parallel trim unit 310-1to 310-N has a predetermined equivalent resistance at default (R_(S)*M)that is equal to the total resistance provided by combining resistors401, 402 and 404 in series (i.e., switch 405 is closed and switch 404 isopen at default). When switch 403 (S1) is closed and switch 405 (S2) isopened in response to control signals C11 and C12, respectively, theresistance of unit 310-1 is reduced to the sum of resistors 401 and 402.When both switch 403 (S1) and switch 405 (S2) are opened, unit 310-1 isopened and has a high impedance. By selectively turning on/off switchesSi and S2 of each unit 310-1 to 310-N, various equivalent resistancescan be achieved. For example, at default the equivalent resistance maybe R_(S)*M/N, with each of the N parallel units 310-1 to 310-N having adefault resistance of R_(S)*M. By opening switch S2 for K units (e.g.,units 310-1 to 310-K, where K<N), and with switch S1 defaulted open, theequivalent resistance of series resistor 155 becomes R_(S)*M/(N-K),which is greater than R_(S) if M/(N-K)>1, and less than R_(S) ifM/(N-K)<1. Turning on the switch S1 in additional trim units willprovide a finer resolution for controlling the resistance R_(S). In oneembodiment, tuner circuit 160 (FIG. 1) includes a logic circuit thatgenerates a pre-selected sequence of control signals CN1, CN2 thaton/off switches S1 and S2 in each unit 310-1 to 310-N until the desiredresistance R_(S) is achieved. Note that switches S1 and S2 in each unit310-1 to 310-N are implemented using CMOS transmission gates.

FIG. 5 is a simplified circuit diagram showing an IC 200 including aline driver 202 according to a second embodiment of the presentinvention. Line driver 202 functions in a manner similar to line driver102 (see FIG. 1), and elements that are essentially common to bothcircuits (e.g., current source 110, amplifier 120, transistors 130 and135, and feedback resistor 153) are identified with the same referencenumbers and are not discussed in detail below for brevity. Similar toline driver 102, line driver 202 includes a bridge resistor 253 and aseries (adjustable) resistor 255. However, unlike line driver 102, linedriver 202 includes an additional series resistor 257 that is connectedbetween a first output node 245 and a second output node 247, which isconnected to the associated transmission line (represented by loadresistance R_(L)). With the addition of second series resistor 257, theoutput resistance ROUT is determined as set forth in Equation 4 (below):

R _(OUT) =R _(SL) +R _(S)/(1+N)   Eq. 4

Further, the addition of series resistor 257 forms a voltage dividerthat changes output voltage V_(OUT) as set forth in Equation 5 (below):

V _(OUT) =I _(DAC) *R _(F) *R _(L)/(R _(SL) +R _(L))   Eq. 5

To achieve the proper termination and balance, the predetermined numberN, load resistance value R_(L), bridge resistance value R_(B), andseries resistance value R_(SL) are matched such that bridge value R_(B)is equal to ratio N multiplied by a sum of load resistance value R_(L)and series resistance value R_(SL), as set forth in Equation 6 (below):

R _(B)=(R _(SL) +R _(L))*N   Eq. 6

Series resistor 257 is added mainly to facilitate the function of echocancellation, which if the output is a fully differential circuit (e.g.,as described below with reference to FIG. 6), it is fully cancelled atthe receiving end.

FIG. 6 depicts a system 300 forming one embodiment of a fullydifferential circuit in which the echo cancellation function of linedriver 202 (FIG. 5) is implemented. System 300 includes an integratedcircuit 200A including a first line driver 202-1 and a second linedriver 202-2 that are respectively connected to transmission lines TL1 &TL2, and an echo cancellation circuit 301 that is connected betweenrespective output nodes of first and second line drivers 202-1 and202-2. Note that associated transmission lines TL1 & TL2 are representedby respective load resistances RL1 and RL2, and form a loadingcapacitance CL. In this configuration, two identical output drivers202-1 and 202-2 (i.e., each driver 202-1 and 202-2 is identical to linedriver 200 of FIG. 5) are employed to deliver a fully differentialoutput signal at the amplifier output voltages V_(X), −V_(X) at outputnodes 245-1 and 245-2, respectively, and at load output voltages V_(Y),−V_(Y) at output nodes 247-1 and 247-2, respectively. Echo cancellationresistive network (circuit) 301 establishes a resistive divider betweenV_(X) and −V_(Y). In the disclosed embodiment, echo cancellation circuit301 includes a first resistor 302 connected between (first) output node245-1 and a first external node N1, a second resistor 303 connectedbetween (second) output node 247-1 and a second external node N2, athird resistor 304 connected between second external node N2 and a thirdexternal node N3, a first capacitor 305 connected between (second)output node 247-1 and third external node N3, a fourth resistor 306connected between (third) output node 245-2 and third external node N3,a fifth resistor 307 connected between (fourth) output node 247-2 and afourth external node N4, a sixth resistor 308 connected between fourthexternal node N4 and first external node N1, and a second capacitor 309connected between (fourth) output node 247-2 and first external node N1.The resistive values of resistors 301-304 and 306-308 are indicated nextto each resistor, and are proportional to resistance values R_(SL) andR_(L) of line drivers 202-1 and 202-2 (as described above), but with ascale up factor M (where M approximately equals 100). The output voltageV₁ can be independent of voltage V_(X) if a full differential signal ispresent. Similarly, V₂ is independent of V_(X), so the echo cancellationis achieved at input V_(IN). The same scaling factor can be applied tothe loading capacitance C_(L) to achieve the cancellation with widebandwidth (i.e., capacitors 305 and 309 have the values indicated inFIG. 6).

For good matching termination R_(OUT) needs to be equal to R_(L) overall process range, this means a tuner is needed to adjust seriesresistance R_(S) to achieve the balance indicated in Equation 7 (below):

R _(SL) +R _(S)/(1+N)=R _(L)   Eq. 7

Equation 7 implies that the resistance of series resistor 255 is equalto the load resistance minus the second series resistance R_(SL), thatsum multiplied by one plus the aspect ratio value N, as set forth by therelationship indicated in Equation 8 (below):

R _(S)=(R _(L) −R _(SL))*(1+N)   Eq. 8

Equation 8 can be rewritten as set forth below in Equations 8-1 and 8-2:

R _(S) +R _(SL)*(1+N)=R _(L)*(1+N)   Eq. 8-1

[R _(S)/(1+N)]+R _(SL) =R _(L)   Eq. 8-2

Because load resistance R_(L) is provided by an external resistor with aresistance value that is independent of process and temperature, andR_(SL) is provided by internal series resistor 257, which has adependency on process and temperature, a tuner circuit is needed notonly to adjust to the desired value of series resistance R_(S), but alsocapable of compensating the characteristic difference (such astemperature effect) between the internal resistances (i.e., R_(S) andR_(SL)) and the external resistance (i.e., R_(L)). Equations 8-1 and 8-2show that all the imperfection such as variations in N and R_(SL) can becompensated by tuning the R_(S) value.

FIG. 7 is a simplified circuit diagram showing a tuner circuit 260 fortuning series resistor 255 to implement Eq. 7 (above). In this circuit,resistance R_(EXT) represents an external resistor (shown in FIG. 8(A))having the same character (such as temperature effect) as that of loadresistance RL, and all the remaining resistances are implemented byinternal resistors (i.e., resistors formed on the substrate used tofabricate IC 200, see FIG. 5). As shown in FIG. 8(A), current sources261 and 262 are controlled by a signal generating circuit 310 that usesa fixed bandgap voltage reference V_(BG) and external resistanceR_(EXT), along with P-channel transistors having aspect ratios “1” and“N” as shown, where N is the same aspect ratio value associated withtransistors 130 and 135 (see FIG. 5). The current generated by currentsource 261 is thus N times the current generated by current source 262.Resistors 265 and 267 have resistances R_(S), and R_(SL′) that arereplica versions of resistors 255 and 257 with a scale ratio. Thevoltage at node 268 is therefore V_(BG)/R_(EXT)*(R_(S′)+(1+N)*R_(SL′)).Another current source 271 is controlled by a signal generating circuit320, shown in FIG. 8(B), where the signal is generated from the bandgapvoltage reference V_(BG) over an internal resistance R_(A1) multipliedby a factor (1+N). As indicated in FIG. 7, this current flows tointernal resistances ΔR (resistor 272) and R_(A2) (resistor 273),generating node voltages 274 and 275. Node voltage 275 across resistor273 is V_(BG)/R_(A1)*(1+N)*R_(A2). Resistor 272 (resistance ΔR) isdesigned to be a relatively small, so node voltages 274 and 275 are veryclose with node voltage 274 slightly higher. Two comparators 276 and 277and a look-up table 279 are employed to generate the control signal onbus 269, which is used to tune both series resistor 255 (FIG. 5) andreplica series resistor 265. Comparator 276 is set such that if the nodevoltage 268 is higher than node voltage 274, it outputs a high pulse“DN” (down) to look-up table 279. Conversely, comparator 277 is set suchthat if the node voltage 268 is lower than node voltage 274, it outputsa low pulse “UP” to look-up table 279. The DN and UP signals causelook-up control table 279 to adjust the resistance of replica seriesresistor 265 (resistance R_(S′)) to increase or decrease the voltage onnode 268. The whole operation achieves a negative feedback loop suchthat the node voltage 268 is kept in between the node voltages 274 and275. After cancelling out the V_(BG) term on both sides of resistor 265,the net result of this loop is to generate the functionR_(S′)/(1+N)+R_(SL′)=β*R_(EXT), where β is a constant set by resistancesR_(A2)/R_(A1). By properly choosing the scale factor and setting the βvalue such that β*R_(EXT)=(1+N)*R_(L), tuner circuit 260 achieves thereplica control that satisfies Equation 8 (above); that is, the outputof look-up table 279 tunes series resistor 255 (FIG. 5) to the desiredvalue. In one embodiment, look-up table 279 contains a series ofpre-selected control signal combinations that adjust the resistance ofRs′ with the proper resolution. The loop does not need a calibrationcycle and does not require a clock signal, so tuner circuit 260 mayremain on (active) all the time to adjust for temperature andenvironment changes. Alternatively, by adding another 2*(M+K) latchcircuit (not shown in FIG. 7), the selection can be locked and the tunerbe powered down.

Although the present invention has been described with respect tocertain specific embodiments, it will be clear to those skilled in theart that the inventive features of the present invention are applicableto other embodiments as well, all of which are intended to fall withinthe scope of the present invention.

1. A line driver for generating a predetermined output voltage on anoutput node of an integrated circuit when the output node is connectedto a transmission line having a first resistance value, the line drivercomprising: means for generating an output control signal in response toa digital data signal, a first stage transistor for generating a firstcurrent at an internal node in response to the output control signal, asecond stage transistor for generating a second current at the outputnode in response to the output control signal, wherein the second stagetransistor is constructed such that the second current is apredetermined number times larger than the first current, a bridgeresistor connected between the internal node and a common mode voltage;and a series resistor connected between the internal node and the outputnode, wherein the bridge resistor has a second resistance value set suchthat an internal voltage at the internal node is equal to thepredetermined output voltage generated at the output node, wherebysubstantially zero current flows between the output node and theinternal node through the series resistor.
 2. The line driver accordingto claim 1, wherein the second resistance value of the bridge resistoris substantially equal to the predetermined number multiplied by thefirst resistance value of the transmission line.
 3. The line driveraccording to claim 1, further comprising a feedback resistor having athird resistance value that is connected between said internal node andsaid means for generating the output control signal such that saidfeedback resistor and said bridge resistor form a bridge circuit, andwherein the second resistance value of the bridge resistor and the thirdresistance value are matched such that the voltage at the internal nodeis equal to the first current times the predetermined number times thefirst resistance value of the transmission line.
 4. The line driveraccording to claim 1, wherein the series resistor has a resistance valuesubstantially equal to (1+N)*R_(L), where N denotes the predeterminednumber, and where R_(L) denotes the first resistance value of thetransmission line.
 5. The line driver according to claim 1, wherein theseries resistor comprises a plurality of parallel trim units, wherein aunit resistance value of each of said plurality of parallel trim unitsis adjustable such that a combined equivalent resistance of saidplurality of parallel trim units is equal to a predetermined resistancevalue.
 6. The line driver according to claim 1, further comprising asecond series resistor connected to the output node such that the secondseries resistor is connected between the output node and thetransmission line.
 7. The line driver according to claim 6, wherein saidsecond series resistor has a third resistance value, and wherein thepredetermined number, the first resistance value of the transmissionline, the second resistance value of the bridge resistor and the thirdresistance value are matched such that the second resistance value isequal to said predetermined number multiplied by a sum of the firstresistance value and the third resistance value.
 8. The line driveraccording to claim 7, wherein the series resistor has a resistance valuesubstantially equal to (1+N)*(R_(L)−R_(SL)), where N denotes thepredetermined number, where R_(L) denotes the first resistance value ofthe transmission line, and where R_(SL) denotes the third resistancevalue of the second series resistor.
 9. A line driver for generating apredetermined output voltage on an output node of an integrated circuitwhen the output node is connected to a transmission line having a firstresistance value, the line driver comprising: means for generating anoutput control signal in response to a digital data signal, a firststage transistor for generating a first current at an internal node inresponse to the output control signal, a second stage transistor forgenerating a second current at the output node in response to the outputcontrol signal, wherein the second stage transistor is constructed suchthat the second current is a predetermined number times larger than thefirst current, a bridge resistor connected between the internal node anda common mode voltage; a series resistor connected between the internalnode and the output node; and means for adjusting a total outputresistance value of the line driver such that the total outputresistance value is equal to the first resistance value of thetransmission line.
 10. The line driver according to claim 9, wherein theseries resistor comprises a plurality of parallel trim units, wherein aunit resistance value of each of said plurality of parallel trim unitsis adjustable such that a combined equivalent resistance of saidplurality of parallel trim units is equal to a predetermined resistancevalue.
 11. The line driver according to claim 10, wherein said meanscomprises a control circuit for transmitting a plurality of controlsignals to said plurality of parallel trim units until said combinedequivalent resistance is equal to said predetermined resistance value.12. The line driver according to claim 9, wherein the series resistorhas a resistance value substantially equal to (1+N)*R_(L), where Ndenotes the predetermined number, and where R_(L) denotes the firstresistance value of the transmission line.
 13. The line driver accordingto claim 9, further comprising a second series resistor connected to theoutput node such that the second series resistor is connected betweenthe output node and the transmission line, wherein said second seriesresistor has a third resistance value, and wherein the series resistorhas a resistance value substantially equal to (1+N)*(R_(L)−R_(SL)),where N denotes the predetermined number, where R_(L) denotes the firstresistance value of the transmission line, and where R_(SL) denotes thethird resistance value of the second series resistor.
 14. The linedriver according to claim 9, wherein the bridge resistor has a secondresistance value set such that an internal voltage at the internal nodeis equal to the predetermined output voltage generated at the outputnode, whereby substantially zero current flows between the output nodeand the internal node through the series resistor.
 15. A systemcomprising: an integrated circuit including: a first line driverincluding a first output node, a second output node, a first seriesresistor connected between the first output node and the second outputnode, and means for generating a first output signal on the first outputnode, whereby a second output signal is generated on the second outputnode, and a second line driver including a third output node, a fourthoutput node, a second series resistor connected between the third outputnode and the fourth output node, and means for generating a third outputsignal on the third output node, whereby a fourth output signal isgenerated on the fourth output node, wherein the first output signal andthe third output signal are differential signals with respect to eachother; first and second transmission lines respectively connected to thesecond output node and the fourth output node; and an echo cancellationcircuit comprising: a first resistor connected between the first outputnode and a first external node, a second resistor connected between thesecond output node and a second external node, a third resistorconnected between the second external node and a third external node, afirst capacitor connected between the second output node and the thirdexternal node, a fourth resistor connected between the third output nodeand the third external node, a fifth resistor connected between thefourth output node and a fourth external node, a sixth resistorconnected between the fourth external node and the first external node,and a second capacitor connected between the fourth output node and thefirst external node.